Full-chip vectorless dynamic power integrity analysis and verification against 100uV/100ps-resolution measurement

Abstract

The advances in semiconductor manufacturing, EDA tools, and VLSI design technologies are enabling circuit designs with increasingly higher speed and density. However, this trend is causing the on-chip power distribution network to experience larger dynamic voltage fluctuations due to dynamic voltage drop, L di/dt noise, and/or LC resonance. As a result, the analysis of power-integrity, as well as the evaluation and calibration of the analysis methodology, has become a major challenge in designing high-performance circuits. An innovative vectorless dynamic power-ground noise analysis approach is discussed in this paper. This approach addresses full-chip complexity with transistor-level accuracy. This analysis approach demonstrated very good correlation with an on-chip supply noise measurement in 0.13-/spl mu/m CMOS technology, capable of achieving 100 /spl mu/V/100 ps resolution.