Layout Role in Failure Physics of IGBTs Under Overloading Clamped Inductive Turnoff

Abstract

The clamped inductive turnoff failure of nonpunchthrough insulated-gate bipolar transistors (IGBTs) is investigated under overcurrent and overtemperature events. First, their electrical and physical signatures are experimentally determined. Second, physical TCAD simulations are carried out considering the current mismatch among the cells from the chip core, gate runner, and edge termination areas. As a result, a secondary breakdown of the IGBT periphery cells at the edge of the gate runner has been identified to be responsible for the failure.