IEEE Journal of Solid-State Circuits · 1989 · 14 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignHigh-frequency Semiconductor DevicesIntegrated Circuit DesignInterconnect DesignLow-power Digital Circuit DesignCmos Logic CircuitsDemultiplexersGallium ArsenideGallium Arsenide Field-effect TransistorsVlsi Implementation
A 12:1 multiplexer and 11:2 demultiplexer that operate at up to 3 Gb/s are discussed. The circuits were fabricated with a 1- mu m-design-rule silicon NMOS VLSI technology and operate from a 3.5-V power supply. The multiplexer chip has 200 gates and dissipates 0.5 W of power. The demultiplexer chip has 400 gates and dissipates 0.75 W. Performance of these devices compares well in both speed and power to the best gallium-arsenide results reported to date.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
6
Gigabit Logic Circuits with Scaled nMOS
D.L. Fraser, H.J. Boll, R. Bayruns et al. · European Solid-State Circuits Conference · 1981 · 21 citations
Engineering, Computer Engineering, Electrical Engineering +17
Gigabit Logic Circuits with Scaled nMOS
Fraser, Boll, Bayruns et al. · European Solid-State Circuits Conference · 1981 · 12 citations
Engineering, Computer Engineering, Electrical Engineering +17