The analysis and design of CMOS multidrain logic and stacked multidrain logic

Abstract

A CMOS logic circuit called the CMOS multidrain logic (MDL) is proposed, analyzed, and experimentally observed. The basic circuit structure, which is derived from integrated injection logic, consists of an enhancement-mode MOSFET as a current injector and a multidrain MOSFET with drain terminals as output nodes and the gate terminal as input node. As compared with the multidrain NMOS logic, the difference is that an enhancement MOS instead of a depletion NMOS is used as a current injector.