2008 · 24 citations · 3 references
EngineeringComputer EngineeringElectrical EngineeringMemoryMicroelectronicsSemiconductor DevicesCmos Circuit DesignLeakage Power ReductionMemory DevicesFlash MemoryGate LeakageGate-induced Drain LeakageMemory Circuit DesignNand Flash MemoryReduction Of AreaSource-drain LeakageStorage Capacity
NAND flash memory use in digital still cameras and cellular phones is driving demand for larger-capacity storage. Moreover, NAND flash has the potential to replace HDDs. To achieve larger capacity while maintaining low cost per bit, technical improvements in feature size and area reduction are essential. To meet the stringent requirements, we develop a 16 Gb 4-level NAND flash memory in 43 nm CMOS technology. In 43 nm generation, gate-induced drain leakage (GIDL) influences the electrical field on both sides of NAND strings. GIDL causes severe program disturb problems to NAND flash memories. To avoid GIDL, two dummy wordlines (WL) on both sides of NAND strings are added. This is effective because the dummy gate voltages, are selected independent of the program inhibit voltage.
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A 146mm/sup 2/ 8Gb nand flash memory with 70nm CMOS technology
T. Hara, Koichi Fukuda, K. Kanazawa et al. · 2005 · 21 citations
Engineering, Computer Engineering, Electrical Engineering +17