Japanese Journal of Applied Physics · 1985 · 23 citations · 6 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDelay ModelingDigital Logic DesignTiming AnalysisCmos Logic CircuitsDigital Logic CircuitsHigh-speed Cmos DesignHigh-speed Logic DesignJosephson JunctionsLogic Gate DelayThreshold CircuitsThreshold Logic
A Josephson logic OR gate suitable for high speed logic circuits is proposed and tested. This gate has a structure modified from Variable Threshold Logic (VTL) to obtain large operating margin and small occupation area. The operating margin is calculated as ±19% for fan-out of 2, even with the critical current variation of ±20%. The circuit area is 40×60 µm 2 . A chain of 5-stage OR gates was fabricated. The gates had Josephson junctions of 4 µm and 7 µm diameter made with Pb-alloy technology. The minimum gate delay of 9 ps was measured using a Josephson sampler.
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Logic delays of 5-μm resistor coupled Josephson logic
J. Sone, Taichi Yoshida, S. Tahara et al. · Applied Physics Letters · 1982 · 17 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +17