Japanese Journal of Applied Physics · 1983 · 14 citations · 11 references
EngineeringComputer EngineeringElectrical EngineeringMicroelectronicsSemiconductor DevicesVlsi DesignCmos Circuit DesignDelay ModelingDigital Logic DesignLow-power Digital Circuit DesignTiming AnalysisCircuit Delay ModelingGate Delay ModelingJosephson JunctionsLogic Gate DelayLogic Gate NetworksLow-power Logic DesignSwitching DelaySwitching Delay Analysis
Sub-10 ps logic delays have been obtained in a Josephson four junction logic (4JL) gate. An experimental circuit including a logic chain of ten 4JL gates whose minimum junction size is 2.5 µm square has been fabricated using a Pb-alloy integration technology. The shortest switching delay has been measured to be 7 ps/gate for the fanout of 1 with a power dissipation of 4 µW/gate.
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Josephson quantum interference computer devices
H. H. Zappe · IEEE Transactions on Magnetics · 1977 · 103 citations