Source optimization and mask design to minimize MEEF in low k 1 lithography

Abstract

Mask Error Enhancement Factor (MEEF) plays an increasingly important role in the DFM flow required to continue shrinking designs in the low-k₁ lithography regime. The ability to understand and minimize MEEF during design optimization and RET application is essential to obtain a usable process window. The traditional limited-cutline approach to analyzing and characterizing MEEF is no longer sufficient to accommodate increasing design complexity. In this paper, we present a new method of edge-based MEEF for analyzing and characterizing MEEF-based hot spots that overcomes the limitations of the traditional cutline approach. Application of the technique to analyze full-field pixel-based two dimensional (2D) MEEF color maps of several different design clips is explained. Process window (PW) is the most important metric in lithography simulations for evaluating the performance of a given RET solution. Traditionally, process window calculation assumes a perfect mask, with no mask errors or corner rounding. In a low k₁ regime, MEEF increases enough that mask errors can no longer be ignored in PW evaluation. A method of calculating "MEEF-aware" common process windows and creating a MEEF-aware process variation (PV) band, including mask bias, is presented, and wafer image variability is examined under several process variations, including dose, defocus and mask error. Results of MEEF-aware source-mask optimization (SMO) and design rule exploration using inverse lithography technology (ILT) are also presented.