Analysis, Design, and Evaluation of LDMOS FETs for RF Power Applications up to 6 GHz

Abstract

The analysis, design, and evaluation of medium-voltage laterally diffused metal oxide semiconductor (LDMOS) transistors for wireless applications up to 6 GHz is presented. Using an optimized N-LDMOS transistor, power devices of different transistor geometries were fabricated in a standard 0.25-μm bipolar complementary metal oxide semiconductor (BiCMOS) technology with and without on-chip stabilization networks. The influences of the finger geometry and the stabilization networks on the RF performance were studied based on small-signal and large-signal on-wafer measurements. It was analytically shown and experimentally verified that transistor geometries with reduced gate width per finger but higher number of fingers are advantageous regarding the maximum oscillation frequency. From the source/load-pull characterization of a 1.8-mm total gate-width device, state-of-the-art, large-signal performance with a maximum output power of 29.7 dBm and a peak drain efficiency of 44% were obtained at 5.8 GHz. Power evaluation of the LDMOS transistors was also carried out in designed hybrid power amplifier modules targeted for vehicular wireless LAN applications. In the 5.8-5.9 GHz band, an output power of 1 W at 1-dB power compression, an adjacent channel power ratio of -38 dBc and an error vector magnitude of 3% at 1 dB peak power compression are reported.