A new approach to power estimation and reduction in CMOS digital circuits

Leakage current mechanisms and leakage reduction techniques in deep-submicrometer CMOS circuits

Kaushik Roy, Subhas Chandra Mukhopadhyay, Hamid Mahmoodi · Proceedings of the IEEE · 2003 · 2.3K citations

Engineering, Computer Engineering, Electrical Engineering +17

A neutral netlist of 10 combinational benchmark circuits and a target translator in FORTRAN

F. Brglez · Medical Entomology and Zoology · 1985 · 1.3K citations

Engineering, Computer Engineering, Computer Science +10

Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits

Harry Veendrick · IEEE Journal of Solid-State Circuits · 1984 · 758 citations

Engineering, Computer Engineering, Electrical Engineering +17

Estimation of average switching activity in combinational logic circuits using symbolic simulation

José Monteiro, Srinivas Devadas, Abhijit Ghosh et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1997 · 83 citations

Engineering, Computer Engineering, Electrical Engineering +16

An analytical model for current, delay, and power analysis of submicron CMOS logic circuits

Anas A. Hamoui, N.C. Rumin · IEEE Transactions on Circuits and Systems II Analog and Digital Signal Processing · 2000 · 65 citations

Engineering, Computer Engineering, Electrical Engineering +17