Gate-level Power Estimation

Gate-Level Power Estimation is a computational methodology within electronic design automation that, as a distinct type of power estimation technique, operates at the logic gate level of a circuit to quantify dynamic and static power consumption by analyzing signal transitions and gate characteristics under specified operating conditions.

92

Publications

3.8K

Citations

232

Authors

96

Institutions

Publications per year

2017–2026

7

Authors

232

  1. FN
    Farid N. Najm

    University of Toronto, Canada

    7 publications · 1K citations

    7

    h-index

  2. FV
    Frank Vahid

    University of California, Riverside, United States

    4 publications · 100 citations

    4

    h-index

  3. JH
    Jörg Henkel

    Karlsruhe Institute of Technology, Germany

    4 publications · 100 citations

    4

    h-index

  4. TG
    Tony Givargis

    University of California, Irvine, United States

    4 publications · 100 citations

    4

    h-index

  5. MI
    M.J. Irwin

    Pennsylvania State University, United States

    3 publications · 115 citations

    3

    h-index

1–5 of 232

Venues

  1. 7

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  2. 5

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  3. Integration

    4 publications · 63 citations

    4

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  4. ACM Transactions on Design Automation of Electronic Systems

    TODAES · 3 publications · 80 citations

    3

    h-index

  5. 2

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1–5