Gate-level Power Estimation
Gate-Level Power Estimation is a computational methodology within electronic design automation that, as a distinct type of power estimation technique, operates at the logic gate level of a circuit to quantify dynamic and static power consumption by analyzing signal transitions and gate characteristics under specified operating conditions.
92
Publications
3.8K
Citations
232
Authors
96
Institutions
Publications per year
2017–2026
7
Parents
92
Power estimation for high level synthesis
P. Landman, Jan M. Rabaey · 2002 · 125 citations
Engineering, Computer Engineering, Electrical Engineering +15
Power estimation in sequential circuits
Farid N. Najm, Shashank Goel, I.N. Hajj · 1995 · 95 citations
Engineering, Computer Engineering, Electrical Engineering +14
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232
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96
University of Illinois Urbana-Champaign
Urbana, United States
10 h-index
16 publications
1.5K citations
Princeton University
Princeton, United States
6 h-index
12 publications
1.6K citations

Pennsylvania State University
State College, United States
5 h-index
12 publications
387 citations
University of Southern California
Los Angeles, United States
4 h-index
9 publications
264 citations
The University of Texas at Austin
Austin, United States
4 h-index
10 publications
358 citations
University of California, Riverside
Riverside, United States
4 h-index
7 publications
151 citations
Rutgers, The State University of New Jersey
New Brunswick, United States
3 h-index
4 publications
121 citations
Stanford University
Stanford, United States
3 h-index
6 publications
200 citations
1–8 of 96
7 publications · 958 citations
7
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5 publications · 186 citations
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4 publications · 63 citations
4
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TODAES · 3 publications · 80 citations
3
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2 publications · 40 citations
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1–5