Power estimation for high level synthesis

Abstract

Techniques for rapidly and accurately estimating power consumption based on high level descriptions of system architectures are described. This approach, based on stochastic modeling of bus statistics, achieves the accuracy traditionally associated with gate and circuit level estimation tools while exploiting the reduced computational complexity offered by the architectural level of abstraction. The results presented indicate an estimation accuracy within 9.4% of gate level simulations, while existing high level techniques can be off 80% or more.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>