Ball Grid Array (BGA) Solder Joint Intermittency Detection: SJ BIST

Abstract

This paper presents test results and specifications for SJ BIST™, an innovative sensing method for detecting faults in solder-joint networks that belong to the I/O ports of field programmable gate arrays (FPGAs), especially in ball grid array packages. It is well-known that fractured solder joints typically maintain sufficient electrical contact to operate correctly for long periods of time. Subsequently the damaged joint begins to exhibit intermittent failures: the faces of a fracture separate during periods of stress, causing incorrect FPGA signals. SJ BIST detects faults of 100 Ω or lower with zero false alarms: minimum detectable fault period is one-half the period of the FPGA clock; guaranteed detection is two clock periods. Being able to detect solder joint faults in FPGAs increases fault coverage and health management capabilities, and provides support for condition-based and reliability-centered maintenance.