IEEE Transactions on Computers · 1990 · 13 citations · 18 references
EngineeringComputer EngineeringElectrical EngineeringCircuit TheoryFault-tolerant ComputingMicroelectronicsCmos Circuit DesignDevice ReliabilityJitter AnalysisNoise In Electronic DevicesTiming AnalysisTiming ModelingClock Jitter ModelingFlip-flop ArchitectureFlip-flop DesignIntegrated Circuit NoiseJitterJitter ModelingMetastability AnalysisSynchronizers
A synchronizer timing model, called the jitter model, which has general application to metastable reliability analysis, is proposed and analyzed. The jitter model is applied to show that redundancy cannot improve the metastable reliability of synchronizers, contradicting previous work by A. El-Amawy (see ibid., vol.38, no.5, p.750-3 (1989)). The jitter model extends previous synchronizer input timing models by incorporating the effects of circuit noise. The circuit noise translates into jitter or random time displacement of a previously proposed deterministic aperture mode. The jitter model is supported by simulation, circuit analysis, and experimental work. The results of a SPICE simulation of a CMOS D-type flip-flop are presented. An experimental bistable device is constructed to examine the behavior of synchronizers with noise. Statistical results obtained from the experimental bistable device support the jitter model for metastability. The sensitivity of metastable reliability of redundant synchronizers to modeling assumptions is highlighted.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">></ETX>
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Probability, Random Variables, and Stochastic Processes
Irwin Miller, Anthanasios Papoulis · Technometrics · 1966 · 6.5K citations
Engineering, Mathematics, Physics +14
Analysis and Design of Analog Integrated Circuits
W.R. Betts · Electronics and Power · 1978 · 3.8K citations
Thermal Noise in Field-Effect Transistors
A. Der Ziel · Proceedings of the IRE · 1962 · 345 citations