A New Grain Boundary Model for Drift-Diffusion Device Simulations in Polycrystalline Silicon Thin-Film Transistors

Abstract

We investigated the influence of grain size variations on the device properties of polycrystalline silicon thin film transistors (poly-Si TFTs) by drift-diffusion (DD) simulations. It is shown that subthreshold characteristics in poly-Si TFTs are dependent on the location of grain boundaries when the commonly-used grain boundary model is employed for DD simulations. A more realistic grain boundary model for size variations subject to the Gaussian distribution is proposed. Employing the proposed grain boundary model, threshold voltage variations are naturally represented by the Gaussian distribution expected from the central-limit theorem. The proposed model allows us to quantitatively analyze the device characteristics of poly-Si TFTs.