A low latency wormhole router for asynchronous on-chip networks

Abstract

Abstract—Asynchronous on-chip networks are power efficient and tolerant to process variation but they are slower than syn-chronous on-chip networks. A low latency asynchronous worm-hole router is proposed using sliced sub-channels and the look-ahead pipeline. Channel slicing removes the C-element tree in the completion detection circuit and converts a channel into multiple independent sub-channels reducing the cycle period. The look-ahead pipeline uses the early evaluation protocol to reduce cycle period. Using the lookahead pipeline on the pipeline stages with the maximal cycle period improves the overall throughput. The router is a pure standard cell design implemented by a 0.13 µm technology. The cycle period of the router at the typical corner is 1.7 ns, providing 2.35GByte/sec throughput per port. I.