An ASIC-Ready 1.25–6.25Gb/s SerDes in 90nm CMOS with multi-standard compatibility

Abstract

A small area PHY transceiver that is compatible with CE16G-LR, CE16G-SR, SAS-6G, PCle and XAUl standards is demonstrated. The 4-channel transceiver is realized in a 90 nm CMOS process with each channel occupying a die area of 0.325 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Power dissipation per channel is less than 230 mW from a 1V supply for 6.25 Gb/s, and scales for data rates down to 1.25 Gb/s.