Fine-feature patterning of self-aligned polymeric thin-film transistors fabricated by digital lithography and electroplating

Abstract

Spatially controlled jet-printed etch masks, having a minimum drop size of 40–50μm, were used to define gap patterns having a minimum feature size of ∼10μm. The defined gaps, in combination with nickel electroplating, were used to create bottom-gate electrode thin-film transistors (TFTs) with gate lengths of 10–20μm and gate widths of 150μm. Self-aligned source/drain top contacts were used for fabricating polythiophene-based TFT devices having channel width-to-length ratios of ∼4. A typical p-channel TFT device had an on/off ratio of 107, threshold voltage of −1V, and field-effect mobility of 0.034cm2∕Vs.