Asynchronous interconnect for synchronous soc design

TLDR

System‑on‑chip designs integrate cores and I/O interfaces that operate at different clock frequencies, requiring synchronization that introduces metastability and making multi‑clock chips inherently globally asynchronous. The authors employ asynchronous‑circuit techniques, using a 16‑port, 36‑bit asynchronous crossbar that connects to clock‑domain converters via asynchronous channels, and apply extensive verification and test strategies to ensure robust operation. Their Nexus GALS interconnect localizes PLLs and clock distribution to each synchronous core, improving timing closure and core reusability while providing an elegant, efficient solution to the multi‑clock‑domain problem.

Abstract

System-on-chip (SoC) designs integrate a variety of cores and I/O interfaces, which usually operate at different clock frequencies. Communication between unlocked clock domains requires careful synchronization, which inevitably introduces metastability and some uncertainty in timing. Thus, any chip with multiple clock domains is already globally asynchronous. We have devised a more elegant and efficient solution to the multiple-clock-domain problem. Instead of gluing synchronous domains directly to each other with clock-domain bridges, we use asynchronous-circuit design techniques to handle all clock-domain crossing as well as all cross-chip communication and routing. The phase-locked loop (PLL) and clock distribution can be entirely local to each synchronous core, easing timing closure and improving the reusability of cores across multiple designs. Our solution, Nexus, is a globally asynchronous, locally synchronous (GALS) interconnect that features a 16-port, 36-bit asynchronous crossbar. The crossbar connects through asynchronous channels to clock-domain converters for each synchronous module. To ensure that Nexus will work robustly in a commercial application, we developed and applied many verification and test strategies, including novel variations of noise analysis, timing analysis, and fault and delay testing.