Clock Domain Crossing
Clock Domain Crossing is a synchronization challenge in digital system design wherein signals traverse between distinct clock domains, necessitating specialized circuitry to mitigate metastability and ensure reliable data transfer across asynchronous or frequency-asynchronous clock boundaries.
34
Publications
1.2K
Citations
98
Authors
34
Institutions
Publications per year
2017–2026
3
34
Asynchronous interconnect for synchronous soc design
Andrew Lines · IEEE Micro · 2004 · 121 citations
Point to point GALS interconnect
Simon W. Moore, G. Taylor, Robert Mullins et al. · 2004 · 118 citations
A Scalable Dual-Clock FIFO for Data Transfers Between Arbitrary and Haltable Clock Domains
Ryan W. Apperson, Zhiyi Yu, Michael J. Meeuwsen et al. · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 2007 · 66 citations · Full text
Engineering, Computer Engineering, Electrical Engineering +16
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34
Intel (United States)
Santa Clara, United States
4 h-index
17 publications
386 citations

University of British Columbia
Vancouver, Canada
4 h-index
8 publications
826 citations

Radboud University Nijmegen
Nijmegen, The Netherlands
2 h-index
2 publications
28 citations
Technion – Israel Institute of Technology
Haifa, Israel
2 h-index
5 publications
82 citations

Peking University
Beijing, China
2 h-index
8 publications
92 citations
University of Cambridge
Cambridge, United Kingdom
2 h-index
6 publications
496 citations
Duke University
Durham, United States
2 h-index
5 publications
94 citations

Hong Kong University of Science and Technology
Hong Kong, Hong Kong
1 h-index
4 publications
48 citations
1–8 of 34
2 publications · 77 citations
2
h-index
1 publications · 121 citations
1
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1 publications · 49 citations
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1 publications · 25 citations
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1 publications · 20 citations
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