Superior PBTI Reliability for SOI FinFET Technologies and Its Physical Understanding

Abstract

FinFETs provide a path for continued pitch and voltage scaling because of their excellent electrostatic short channel control. The key to design and optimization of FinFET technologies is to understand the differences of their reliability characteristics from those of planar devices. In this letter, we elucidate the differences in positive-bias temperature instability (PBTI) reliability between silicon-on-insulator nFinFETs and planar-bulk nFETs through experiments and TCAD modeling. We show that significantly improved PBTI for FinFET over planar-bulk at a given operating voltage arises from reduced vertical field. Furthermore, we show that the reduced field in FinFETs stems from less depletion charge in strong inversion associated with a fully depleted structure.