Greedy Tree Growing Heuristics on Block-Test Scheduling Under Power Constraints

A distributed BIST control scheme for complex VLSI devices

Y. Zorian · 2002 · 543 citations

Engineering, Computer Engineering, Electrical Engineering +12

Techniques for minimizing power dissipation in scan and combinational circuits during test application

V. Dabholkar, S. Chakravarty, Irith Pomeranz et al. · IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems · 1998 · 320 citations

Engineering, Computer Engineering, Computer Science +17

REAL: a program for REgister ALlocation

Fadi Kurdahi, Alice C. Parker · 1987 · 312 citations

Architecture, Computer Engineering, Design Automation +12

Minimized power consumption for scan-based BIST

Stefan Gerstendörfer, Hans-Joachim Wunderlich · 2003 · 301 citations

Engineering, Computer Engineering, Electrical Engineering +17

Scheduling tests for VLSI systems under power constraints

R.M. Chou, Kewal K. Saluja, Vishwani D. Agrawal · IEEE Transactions on Very Large Scale Integration (VLSI) Systems · 1997 · 288 citations · Full text

Engineering, Computer Engineering, Electrical Engineering +16