Cycling endurance optimization scheme for 1Mb STT-MRAM in 40nm technology

Abstract

Spin-transfer-torque (STT) MRAM is considered as a good candidate for next-generation memory that can replace Flash, SRAM and DRAM as well. As a replacement of SRAM or DRAM, write endurance more than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">12</sup> cycles is required. However, due to limitation in the reliability of magnetic tunnel junction (MTJ), the required endurance may not be achieved if the MTJ is overstressed by the write voltage. In this paper, a new write-path design with wire-resistance-balance scheme is presented that minimizes the voltage stress on MTJ during write operation for cells near the write buffer. Simulation shows the voltage across MTJ becomes more uniform for cells from top to bottom of array. This new scheme is implemented into 1Mb MRAM test-chip and is fabricated in TSMC 40nm low-power process. Cycling testing shows that write endurance can be improved as compared to the previous design.