2012 · 11 citations · 4 references
Phase ErrorEngineeringClock RecoveryMixed-signal Integrated CircuitComputer EngineeringDigital PhaseDigital PllFrequency ControlFaraway Phase NoiseSignal ProcessingSignal IntegrityAnalog-to-digital Converter
This paper presents a digital phase locked loop (DPLL) with two-step closed-locking technique. The two-step locking allows us to use a simple phase detector, which achieves wide phase detect range and has no complex circuits for glitch compensation. The DPLL has three digital controlled oscillators (DCO) for multi-mode/multi-band operation. The DPLL covers GSM quad-band, and several bands of WCDMA / LTE. The DPLL improves a close-in noise by 17 dB compared with the conventional count-assisted locking, which causes glitch error substantially. The phase error is less than 3.0 degrees in all bands for various conditions. The faraway phase noise is -165dBc/Hz at 20MHz, -161dBc/Hz at 190MHz, and -158dBc/Hz at 120MHz in each TX output, respectively.
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All-digital PLL and transmitter for mobile phones
Robert Bogdan Staszewski, J. Wallberg, S. Rezeq et al. · IEEE Journal of Solid-State Circuits · 2005 · 619 citations