Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS

Abstract

We propose a new multirate architecture of an all-digital PLL (ADPLL) featuring phase/frequency modulation capability. While the ADPLL approach has already proven its benefits of power dissipation and cost reduction through the discrete-time operation and full RF-SoC integration in nanoscale CMOS, the coarse discretization of the phase detector function tends to keep it from reaching the ultimate of the RF performance potential. The proposed ADPLL features an arbitrarily high data rate modulation that is independent from the reference frequency. It is also made substantially free from injection pulling and ill-shaped quantization noise of the TDC by means of dithering with dynamic adjustment of differential pair mismatches as well as frequency translation of the feedback clock. Low power techniques, such as speculative clock retiming and asynchronous counter are used. The presented ADPLL is implemented in 65 nm CMOS as part of a single-chip GSM/EDGE RF-SoC. It occupies 0.35 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 32 mA of current at 1.2 V supply in the low frequency band. The measured results show a virtually spur-free operation.