F. Dulger

Spur-Free Multirate All-Digital PLL for Mobile Phones in 65 nm CMOS

Robert Bogdan Staszewski, Khurram Waheed, F. Dulger et al. · IEEE Journal of Solid-State Circuits · 2011 · 71 citations

New Multirate Architecture, Adpll Approach, Engineering +14

A 1.3-V 5-mW fully integrated tunable bandpass filter at 2.1 GHz in 0.35-μm CMOS

F. Dulger, E. Sánchez‐Sinencio, José Silva-Martínez · IEEE Journal of Solid-State Circuits · 2003 · 66 citations

Peak Gain, Radio Frequency, High-frequency Device +7

A 65nm CMOS DCXO system for generating 38.4MHz and a real time clock from a single crystal in 0.09mm²

Danielle Griffith, F. Dulger, G. Feygin et al. · 2010 · 33 citations

Low-power Electronics, Electrical Engineering, Engineering +14

Spur-free all-digital PLL in 65nm for mobile phones

Robert Bogdan Staszewski, Khurram Waheed, S. Vemulapalli et al. · 2011 · 26 citations

Injection Pulling, Vlsi Design, Engineering +10

A 1.5-V Multi-Mode Quad-Band RF Receiver for GSM/EDGE/CDMA2K in 90-nm Digital CMOS Process

Bertan Bakkaloğlu, P. Fontaine, Ahmed N. Mohieldin et al. · IEEE Journal of Solid-State Circuits · 2006 · 25 citations

Lo Buffers, Wireless Communications, Engineering +10