All-digital PLL and transmitter for mobile phones

TLDR

The circuits are part of a single‑chip GSM/EDGE transceiver SoC fabricated in a 90‑nm digital CMOS process and are architected from the ground up to be compatible with deep‑submicron CMOS processes and readily integrable with digital baseband and application processors. We present the first all‑digital PLL and polar transmitter for mobile phones. The design exploits deep‑submicron CMOS advantages—fast MOS switching, fine lithography, precise matching—while avoiding limited voltage headroom, and implements a fully digital transmitter that uses the all‑digital PLL’s wideband direct frequency modulation, digitally regulates amplitude via active NMOS switches, and replaces the conventional VCO‑based synthesizer with a digitally controlled oscillator and time‑to‑digital converter. The transmitter performs GMSK modulation with less than 0.5°/s rms phase error, –165 dBc/Hz phase noise at 20 MHz offset, and 10 µs settling time; the 8‑PSK EDGE spectral mask is met with 1.2 % EVM; it occupies 1.5 mm² and consumes 42 mA at 1.2 V while producing 6 dBm RF output power.

Abstract

We present the first all-digital PLL and polar transmitter for mobile phones. They are part of a single-chip GSM/EDGE transceiver SoC fabricated in a 90 nm digital CMOS process. The circuits are architectured from the ground up to be compatible with digital deep-submicron CMOS processes and be readily integrateable with a digital baseband and application processor. To achieve this, we exploit the new paradigm of a deep-submicron CMOS process environment by leveraging on the fast switching times of MOS transistors, the fine lithography and the precise device matching, while avoiding problems related to the limited voltage headroom. The transmitter architecture is fully digital and utilizes the wideband direct frequency modulation capability of the all-digital PLL. The amplitude modulation is realized digitally by regulating the number of active NMOS transistor switches in accordance with the instantaneous amplitude. The conventional RF frequency synthesizer architecture, based on a voltage-controlled oscillator and phase/frequency detector and charge-pump combination, has been replaced with a digitally controlled oscillator and a time-to-digital converter. The transmitter performs GMSK modulation with less than 0.5/spl deg/ rms phase error, -165 dBc/Hz phase noise at 20 MHz offset, and 10 /spl mu/s settling time. The 8-PSK EDGE spectral mask is met with 1.2% EVM. The transmitter occupies 1.5 mm/sup 2/ and consumes 42 mA at 1.2 V supply while producing 6 dBm RF output power.