IEEE Journal of Solid-State Circuits · 1987 · 19 citations · 10 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureMicroelectronicsSystem-on-chip DesignCmos Circuit DesignImage ProcessingMicroarchitecture DesignPhysical DesignProcessor MicroarchitectureVery-large-scale Integration LayoutArithmetic Logic Unit ArchitectureArithmetic Logic Unit DesignImage Signal ProcessingMotion CompensationParallel Signal ProcessingReal-time Hardware ArchitectureReal-time Processor DesignVlsi Implementation
A microprogrammable real-time video signal processor (VSP) LSI has been developed for constructing a parallel video signal processing system. The VSP LSI employs a flexible multistage pipelined architecture and can handle such sophisticated image signal processing as high-speed edge detection and motion compensation. It contains many operational function units such as an arithmetic logic unit and with absolute value calculation capability, a minimum/maximum value detector, a two-port SRAM, RAM address pointer and clocked bus lines. The VSP LSI has been designed using two different kinds of automatic layout programs. The chip, which was fabricated with a 2.5-/spl mu/m CMOS and double-layer metallization technology, has an area of 9.91/spl times/9.50 mm/SUP 2/ and contains about 48000 MOSFETs. It operates at a clock frequency of 14.3 MHz with a single 5-V power supply and typically consumes 240 mW. An experimental system, using a single VSP LSI chip, has been constructed in order to demonstrate various application capabilities, such as interframe difference operations, high-speed edge detection and motion compensation.
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An LSI adaptive array processor
Toshiki Kondo, T. Nakashima, Masanao Aoki et al. · IEEE Journal of Solid-State Circuits · 1983 · 43 citations
T. Fukushima, Y. Kobayashi, K. Hirasawa et al. · 1983 · 25 citations
Engineering, Computer Engineering, Electrical Engineering +16
An LSI adaptive array processor
T. Sudo, Tsubasa Nakashima, M. Aoki et al. · 1982 · 19 citations
Video signal processor configuration by multiprocessor approach
T. Nishitani, I. Tamitani, H. Harasaki et al. · 2005 · 18 citations