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Fin-Height Effect on Poly-Si/PVD-TiN Stacked-Gate FinFET Performance
18
Citations
20
References
2012
Year
Electrical EngineeringEngineeringFin-height EffectNanoelectronicsI XmlnsTall FinsApplied PhysicsTensile StressSemiconductor Device FabricationElectronic PackagingSilicon On InsulatorMicroelectronics
We compared the electrical characteristics, including mobility and on -state current <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> , of n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -poly-Si/PVD-TiN stacked-gate FinFETs with different fin heights <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> . The mobility was enhanced in devices with taller fins due to increased tensile stress. However, as gate length <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Lg</i> decreases, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">I</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">on</sub> for devices with tall fins becomes worse, probably due to a high parasitic resistance <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Rp</i> . Furthermore, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">V</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> variation increased with increasing <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">H</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> due to rough etching of the fin sidewall. Process technologies for reducing <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Rp</i> and etching technology that yields smooth precise profiles are essential to exploit the high performance of tall FinFETs.
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