2010 · 15 citations · 6 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureLow-power DesignSystem-on-chip DesignMemory HierarchyMemory Hierarchy DesignMemory Subsystem DesignMulticore Processor DesignPower ManagementProcessor Core DesignApplication Processor ArchitectureBandwidthDirect Memory Access ArchitectureEnergy-efficient Memory HierarchiesEnergy-efficient Memory SystemsLow-power Memory ArchitectureMobile Processor DesignOn-chip Memory Hierarchies
A 40 nm 14-core mobile application processor with a 222 mW Full-HD H.264 video decoder and a video/audio multiprocessor is developed. It has 25 power domains. The power switch circuits realize less than 1 ¿s power-up switching while minimizing rush current. The x512b power-efficient stacked DRAM l/F achieves 10.6 GB/S bandwidth.
6
A 160Gb/s interface design configuration for multichip LSI
Takayuki Ezaki, Kazuhiro Kondo, Hiroshi Ozaki et al. · 2004 · 85 citations
Engineering, Computer Engineering, Electrical Engineering +17