Voltage and temperature dependence of random telegraph noise in highly scaled HKMG ETSOI nFETs and its impact on logic delay uncertainty

Abstract

This paper analyzes the extensive variability of random telegraph noise (RTN) responses to gate voltage and temperature in undoped nanoscale nFETs. Using comprehensive RTN measurements to extract the response parameters of >;600 traps, we show that the RTN can induce delay uncertainty in dense low power (i.e., narrow devices and low V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> ) 14-nm technology that may exceed 50% of the nominal delay.