IEEE Electron Device Letters · 1989 · 85 citations · 5 references
EngineeringElectrical EngineeringMaterials ScienceMicroelectronicsSemiconductor DevicesSemiconductor MaterialsDevice CharacterizationDopingIon ImplantationMetal-oxide-semiconductor Field-effect TransistorsMos CapacitorsSemiconductor Device MaterialsAnnealing EffectsCapacitanceCapacitance MeasurementCapacitorsConductanceDepletion RegionDopant ActivationPolysilicon
The C-V characteristics of arsenic-doped polysilicon show a gate-bias dependence of the inversion capacitance and a reduction in the expected value of the inversion capacitance. The characteristics have been investigated with quasistatic and high-frequency C-V as well as conductance measurements of various capacitors that have been subjected to annealing times and temperatures ranging from 900 degrees C/30 min to rapid thermal annealing at 1050 degrees C. The results can be explained by assuming that there is a depletion region forming in the polysilicon due to insufficient activation of the dopant at the polysilicon/oxide surface. The impact of this condition on the device characteristics is shown to be a 20-30% reduction in the G/sub m/ of NMOS transistors with 125-AA Gate oxide thickness.
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Dopant segregation in polycrystalline silicon
Mohammad M. Mandurah, Krishna C. Saraswat, C. R. Helms et al. · Journal of Applied Physics · 1980 · 371 citations
Submicrometer-channel CMOS for low-temperature operation
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