Modeling of Barrier-Engineered Charge-Trapping nand Flash Devices

Abstract

Barrier-engineered charge-trapping NAND Flash (BE-CTNF) devices are extensively examined by theoretical modeling and experimental validation. A general analytical tunneling current equation for multilayer barrier is derived using the Wentzel-Kramers-Brillouin approximation. The rigorously derived analytical form is valid for both electron and hole tunnelings, as well as for any barrier composition. With this, the time evolution (Vt-time) of any BE-CTNF device during programming/erasing can be accurately simulated. The model is validated by experimental results from bandgap-engineered silicon-oxide-nitride-oxide-silicon and various structures using an Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> top-capping layer. Using this model, various structures of BE-CTNF with high-κ tunneling or blocking dielectric are investigated. Finally, the impacts of barrier engineering on incremental-step pulse programming are examined.