Radiation hardened 2Mbit SRAM in 180nm CMOS technology

Abstract

This work presents an asynchronous 2Mbit SRAM designed following radiation hardening by design methodology. The design takes into account the two possible effects that could damage the circuits in harsh environments: cumulative effects due to long-time exposure to radiation and single event effects due to interaction with charged particles. The circuit has been fabricated in an 180nm TowerJazz CMOS process. Post-irradiation measurements of a previous design using the same design methodology confirm that the SRAM is rad-hard up to 760krad of Total Ionizing Dose (TID) for a 100rad/s dose rate.