A 4.5-mW Closed-Loop $\Delta\Sigma$ Micro-Gravity CMOS SOI Accelerometer

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> In this paper, design, implementation and characterization of a 3-V switched-capacitor (SC) &lt;formula formulatype="inline"&gt;&lt;tex&gt;$\Delta\Sigma$&lt;/tex&gt; &lt;/formula&gt; CMOS interface circuit for the closed-loop operation of a lateral capacitive micro-gravity silicon-on-insulator (SOI) accelerometer is presented. The interface circuit is based on a front-end programmable reference-capacitorless SC charge amplifier and a back-end second-order SC &lt;formula formulatype="inline"&gt; &lt;tex&gt;$\Delta\Sigma$&lt;/tex&gt;&lt;/formula&gt; modulator. The accelerometer is fabricated through a dry-release high aspect-ratio reduced-gap process. By incorporating the low-&lt;formula formulatype="inline"&gt;&lt;tex&gt;$Q$&lt;/tex&gt;&lt;/formula&gt; transfer function of the microaccelerometer in a feedback loop, the system's dynamic range is improved by 20 dB, leading to a measured resolution of 4 &lt;formula formulatype="inline"&gt; &lt;tex&gt;$\mu{\hbox{g}}/\surd{\hbox{Hz}}$&lt;/tex&gt;&lt;/formula&gt; and an output dynamic range of 95 dB at 20 Hz. The bias instability is 2 to 8 &lt;formula formulatype="inline"&gt; &lt;tex&gt;$\mu{\hbox{g}}$&lt;/tex&gt;&lt;/formula&gt; for 12 hours. The chip is fabricated in the 0.5-&lt;formula formulatype="inline"&gt;&lt;tex&gt;$\mu{\hbox {m}}$&lt;/tex&gt;&lt;/formula&gt; standard CMOS process with an area of 2.25 &lt;formula formulatype="inline"&gt;&lt;tex&gt;${\hbox {mm}}^{2}$&lt;/tex&gt;&lt;/formula&gt;. The integrated circuit (IC) consumes 4.5 mW of power. </para>