A low power-delay-product and robust Isolated-DICE based SEU-tolerant latch circuit design

Modeling the effect of technology trends on the soft error rate of combinational logic

Premkishore Shivakumar, Michael Kistler, Stephen W. Keckler et al. · 2003 · 1.4K citations

Engineering, Computer Engineering, Electrical Engineering +17

Radiation-induced soft errors in advanced semiconductor technologies

R. Baumann · IEEE Transactions on Device and Materials Reliability · 2005 · 1.4K citations

Engineering, Computer Engineering, Electrical Engineering +17

Upset hardened memory design for submicron CMOS technology

T. Calin, M. Nicolaidis, Raoul Velazco · IEEE Transactions on Nuclear Science · 1996 · 1.1K citations

Engineering, Computer Engineering, Electrical Engineering +14

Radiation-Induced Soft Errors in Advanced Semiconductor Technologies

Robert Baumann · IEEE Transactions on Device and Materials Reliability · 2005 · 976 citations

Engineering, Computer Engineering, Electrical Engineering +17

Collection of Charge on Junction Nodes from Ion Tracks

George C. Messenger · IEEE Transactions on Nuclear Science · 1982 · 692 citations

Engineering, Computer Engineering, Electrical Engineering +17