2006 · 11 citations · 5 references
ComputingComputer EngineeringElectrical EngineeringComputer SecurityHardware SecuritySecurity ArchitectureBuilt-in Self-testCryptographic ArchitectureDesign For TestabilityEmbedded System SecuritySecure System DesignComplexityCryptography TestingEfficiencyImplementation ComplexityLow-power Design For TestabilityScan Chain DesignScan DesignSystem Architecture Design
Scan based design-for-test is a powerful testing scheme, but it can be used to retrieve secrets stored inside a crypto device. In this paper, we propose a novel scan based DFT architecture called secure scan that maintains the high test quality without compromising the security. Moreover our proposition is universal and can be easily implemented as an extension of the standard scan chain architecture. Apart from presenting our proposal we analyse its implementation complexity, test's efficiency impact and gained security level
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David Hély, Marie-Lise Flottes, F. Bancel et al. · 2008 · 102 citations
Scan design and secure chip [secure IC testing]
David Hély, Marie-Lise Flottes, F. Bancel et al. · 2004 · 94 citations · Full text
Bo Yang, Kaijie Wu, Ramesh Karri · 2005 · 59 citations