Scan design and secure chip [secure IC testing]

TLDR

Testing secure systems is a bottleneck because secure chips limit observability and controllability, making verification of correct operation difficult. The paper analyzes the scan technique to expose security vulnerabilities introduced by conventional DfT methods. The authors propose a scan‑secure solution that mitigates the identified vulnerabilities. Using conventional DfT techniques can significantly reduce the security of secure ICs.

Abstract

Testing a secure system is often considered as a severe bottleneck. While testability requires an increase in both observability and controllability, secure chips are designed with the reverse in mind, limiting access to chip content and on-chip controllability functions. As a result, using usual design for testability (DfT) techniques when designing secure ICs may seriously decrease the level of security provided by the chip. This dilemma is even more severe as secure applications need well-tested hardware to ensure that the programmed operations are correctly executed. In this paper, a security analysis of the scan technique is performed. This analysis aims at pointing out the security vulnerability induced by using such a DfT technique. A solution securing the scan is finally proposed.