IEEE Journal of Solid-State Circuits · 1987 · 14 citations · 4 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureLow-power DesignMicroelectronicsDigital Logic DesignLow-power Cache DesignLow-power Digital Circuit DesignMemory DevicesMemory Subsystem DesignTiming AnalysisCache MemoryJosephson JunctionsLatch DesignLow-power Memory ArchitectureLow-power Memory CircuitsMemory Circuit DesignMemory CircuitsSignal Propagation Delay
A 6-b resistor-coupled Josephson logic (RCJL) decoder has been developed for a 1-kb Josephson cache memory. This decoder is an AC-powered latch decoder constructed in a parallel decoding architecture. The 6-b decoder consists of three stages of AND gates and high-drivability OR gates, and direct-coupled inverters generating complement address signals. The decoder is designed to eliminate timing control signals for fast operation. The 6-b decoder, consisting of 248 gates with 1042 Josephson junctions, was fabricated using Pb-alloy technology with 3.5-/spl mu/m minimum linewidth patterns. A /spl plusmn/11% gate-bias current margin was obtained. The shortest decoding time was 280 ps, including 66-ps signal propagation delay along the interconnecting strip line, with 4-mW power dissipation.
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