ESD Phenomena and Protection Issues in CMOS Output Buffers

Abstract

In VLSI devices with 1 μm CMOS technologies the use of silicided diffusions has been found to have a negative impact on the ESD protection levels of both inputs and outputs. In this paper the ESD phenomena for CMOS output buffers is presented to show that it can be improved for advanced processes. The primary findings here show that the p-channel device of the buffer can be made to play a significant role and that this feature can be used to achieve good protection for positive stress with respect to both VDD and VSS.