ESD on CHMOS Devices - Equivalent Circuits, Physical Models and Failure Mechanisms

Abstract

Using new techniques it is possible to construct an EOS/ESD equivalent circuit of a product. Location of energy dissipation during an EOS/ESD event is determined by a pulsed near infrared technique. Rules for predicting location of ESD dissipation are defined. N+-P-N+ structures and n-channel transistors suffer from a current lock-on effect, which is apparently caused by a runaway oxide trapping mechanism. Different failure mechanisms are observed at narrow and wide pulse widths. Hot electron induced damage occurs under mechanical handling conditions. On CMOS outputs the n-channel device absorbs most of the ESD, and is very fragile.