VLSI on-chip interconnection performance simulations and measurements

Abstract

We examine electrical performance issues associated with advanced VLSI semiconductor on-chip interconnections or “interconnects.” Performance can be affected by wiring geometry, materials, and processing details, as well as by processor-level needs. Simulations and measurements are used to study details of interconnect and insulator electrical properties, pulse propagation, and CPU cycle-time estimation, with particular attention to potential advantages of advanced materials and processes for wiring of high-performance CMOS microprocessors. Detailed performance improvements are presented for migration to copper wiring, low-ε dielectrics, and scaled-up interconnects on the final levels for long-line signal propagation.