Design Automation Conference · 1982 · 34 citations · 2 references
EngineeringComputer EngineeringElectrical EngineeringComputer ArchitectureMicroelectronicsVlsi DesignDelay ModelingLogic SynthesisPhysical DesignTiming AnalysisTiming ModelingVery-large-scale Integration LayoutCircuit Delay ModelingDelay SimulationExecution Time AnalysisGate Delay ModelingLogic GatesPropagation Delay Modeling
This paper describes a program for automatically computing the delay through LSI/VLSI chips which have been laid out using automatic layout programs. A unique algoristhm for synthesizing RC networks from artwork data, which significantly reduces execution time and computer storage, is included. A novel and simple method for determining the delay through logic gates due to arbitrary RC network load at the output is also presented and discussed.
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Signal Delay in RC Tree Networks
P. Penfield, J. Rubinstein · CalTechCONF (Cal Tech) · 1981 · 134 citations