IEEE Design & Test of Computers · 2010 · 27 citations · 10 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureDesign OptimizationSystem-on-chip DesignEnergy-efficient Embedded SystemsNetwork-on-chip DesignPower EstimationPower ManagementPower OptimizationPower-aware DesignDynamic Power DissipationEarly-stage Power EstimationInterconnect Power DissipationNetwork-on-chipNetwork-on-chip ArchitecturesPower ModelPower Modeling And EstimationSimulation-based Power Estimation
This model-based methodology and supporting toolset lets designers estimate application-specific network-on-chip (NoC) power dissipation at early stages of the design flow. An actor-oriented simulation framework captures the NoC's dynamic behavior and feeds its parameters to a rate-based power estimation model. Integrating this model into the proposed design flow enables the analysis of different design parameters and the identification of the most power-efficient application platform mappings.
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