Improvement Potential and Equalization Example for Multidrop DRAM Memory Buses

Abstract

For PC DRAM memory buses, the number of slots per channel have been decreased as signal frequencies increase. This limits the data capacity per channel. In this paper, we show that the slot reduction is not due to fundamental limits of the channel structure but due to signaling schemes. An equalization scheme is presented which enables higher bit-rates with minimum modification of bus structure and memory circuits. The circuitry added to the host side of the bus has reasonable complexity and features very low latency. Measurements of memory-to-host transmissions over a four-drop-bus at 2.6 Gb/s using a 0.13 mum CMOS test-circuit is presented.