Jared Zerbe

Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

Jared Zerbe, C. Werner, Vladimir Stojanović et al. · IEEE Journal of Solid-State Circuits · 2003 · 228 citations

Hardware Security, Engineering, Analog-to-digital Converter +9

A portable digital DLL for high-speed CMOS interface circuits

B.W. Garlepp, Kevin Donnelly, Jun Kim et al. · IEEE Journal of Solid-State Circuits · 1999 · 188 citations

Hardware Security, Electrical Engineering, Engineering +13

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

T.H. Lee, Kevin Donnelly, J. Ho et al. · IEEE Journal of Solid-State Circuits · 1994 · 178 citations

Low-power Electronics, Electrical Engineering, Low Jitter +15

Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery

Vladimir Stojanović, A. Ho, B.W. Garlepp et al. · IEEE Journal of Solid-State Circuits · 2005 · 149 citations

Serial Link Transceiver, Engineering, Pam4 System +12

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

Reza Navid, E-Hung Chen, Masum Hossain et al. · IEEE Journal of Solid-State Circuits · 2014 · 85 citations

Low-jitter Clock, Engineering, Clock Recovery +11