Equalization and clock recovery for a 2.5-10-Gb/s 2-PAM/4-PAM backplane transceiver cell

Jared Zerbe, C. Werner, Vladimir Stojanović, +10

IEEE Journal of Solid-State Circuits

Hardware SecurityEngineeringAnalog-to-digital ConverterMultitap Receiver EqualizerSelect Transitions +7

A portable digital DLL for high-speed CMOS interface circuits

B.W. Garlepp, Kevin Donnelly, Jun Kim, +9

IEEE Journal of Solid-State Circuits

Hardware SecurityElectrical EngineeringEngineeringVlsi DesignDual Delay Lines +11

A 2.5 V CMOS delay-locked loop for 18 Mbit, 500 megabyte/s DRAM

T.H. Lee, Kevin Donnelly, J. Ho, +3

IEEE Journal of Solid-State Circuits

Low-power ElectronicsElectrical EngineeringLow JitterVlsi DesignEngineering +13

Autonomous dual-mode (PAM2/4) serial link transceiver with adaptive equalization and data recovery

Vladimir Stojanović, A. Ho, B.W. Garlepp, +8

IEEE Journal of Solid-State Circuits

Serial Link TransceiverEngineeringPam4 SystemMixed-signal Integrated CircuitAdaptive Modulation +10

A 40 Gb/s Serial Link Transceiver in 28 nm CMOS Technology

Reza Navid, E-Hung Chen, Masum Hossain, +11

IEEE Journal of Solid-State Circuits

Low-jitter ClockEngineeringClock RecoveryLower JitterMixed-signal Integrated Circuit +9

A 16 Gb/s/Link, 64 GB/s Bidirectional Asymmetric Memory Interface

Haechang Lee, Kun-Yung Ken Chang, Jung‐Hoon Chun, +17

IEEE Journal of Solid-State Circuits

Link Memory InterfaceElectrical EngineeringEngineeringVlsi DesignMixed-signal Integrated Circuit +11

Adaptive equalization and data recovery in a dual-mode (PAM2/4) serial link transceiver

Vladimir Stojanović, A. Ho, B.W. Garlepp, +6

Transceiver ChipWireless CommunicationsMulti-carrier CommunicationSerial Link TransceiverEngineering +11

A 2 Gb/s/pin 4-PAM parallel bus interface with transmit crosstalk cancellation, equalization, and integrating receivers

Jared Zerbe, P.S. Chau, C. Werner, +6

Equalization TechniquesTransmit Crosstalk CancellationChannel EqualizationComputer EngineeringCommunication Interface +1

A 7.5Gb/s 10-Tap DFE Receiver with First Tap Partial Response, Spectrally Gated Adaptation, and 2nd-Order Data-Filtered CDR

Brian Leibowitz, Jade Kizer, Haechang Lee, +16

Spectrally Gated AdaptationEngineeringEqualization UpdatesData ConverterMixed-signal Integrated Circuit +9

1.6 Gb/s/pin 4-PAM signaling and circuits for a multidrop bus

Jared Zerbe, P.S. Chau, C. Werner, +4

IEEE Journal of Solid-State Circuits

Hardware SecurityEngineeringMultidrop BusMulti-pam SignalingMixed-signal Integrated Circuit +7