Electronics Letters · 1999 · 12 citations · 1 references
EngineeringComputer EngineeringComputer ScienceComputer ArchitectureHardware Description LanguagesMicroelectronicsDelay ModelingDesign For TestabilityHardware Modeling For Digital SystemsLogic SynthesisTiming AnalysisTiming ModelingDelay SimulationDynamic Timing AnalysisGate Delay ModelingPropagation Delay ModelingRegister-transfer Level Timing AnalysisStatic Timing AnalysisTiming Characterization
simulator framework and HDL modelling mechanism needed for its implementation are proposed. The method is implemented using the simulator Alecsis and its efficiency is demonstrated on a set of ISCAS'85 benchmark circuits.
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