A Robust Embedded Ladder-Oxide/Cu Multilevel Interconnect Technology for 0.13 µm Complementary Metal Oxide Semiconductor Generation

Noriaki Oda, S. Ito, T. Takewaki, Kazutoshi Shiba, H. Kunishima, Nobuo Hironaga, Ichiro Honma, Hiroaki Nanba, Shinji Yokogawa, Akiko Kameyama,

Japanese Journal of Applied Physics · 2007 · 11 citations · 1 references

Concepts

Abstract

A robust embedded ladder-oxide (k=2.9)/copper (Cu) multilevel interconnect is demonstrated for 0.13 µm complementary metal oxide semiconductor (CMOS) generation. A stable ladder-oxide intermetal dielectric (IMD) is integrated by the Cu metallization with a minimum wiring pitch of 0.34 µm, and a single damascene (S/D) Cu-plug structure is applied. An 18% reduction in wiring capacitance is obtained compared with that in SiO2 IMDs. The superior controllability of metal thickness by the S/D process enables us to enhance the MPU maximum frequency easily. The stress-migration lifetime of vias on wide metals for the S/D Cu-plug structure is longer than that for a dual damascene (D/D) structure. Reliability test results such as electromigration (EM), the temperature dependant dielectric breakdown (TDDB) of Cu interconnects, and pressure cooker test (PCT) results are acceptable. Moreover, a high flexibility in a thermal design is obtained.

References

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