IEEE Design & Test of Computers · 2001 · 55 citations · 20 references
EngineeringComputer EngineeringComputer ScienceAnalog ElectronicsComputer ArchitectureSystem-on-chip DesignAnalog DesignAnalog Integrated CircuitsBuilt-in Self-testCmos Circuit DesignHierarchical DesignLogic SynthesisAnalog Built-in Self-testAnalog Circuit DesignAutomatic Test Pattern GenerationBuilt-in Self-test For Analog CircuitsCmos Analog Integrated CircuitsCore IntegrationObservabilitySystem Observability
Automatic test-pattern generation (ATPG) algorithms for analog circuits have been under intense investigation for the last several years. As system design aggressively moves to system-on-a-chip (SoC) and core-based integration, hierarchical analog ATPG emerges as an even more difficult challenge. Attempts to develop an effective algorithm have had varying degrees of success. This article reviews some fundamental issues and recent work in hierarchical analog ATPG and presents an algorithm based on controllability and observability computation. This algorithm has been implemented in a prototype tool, and results based on several case studies show the application of the technique.
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