Analog and mixed-signal benchmark circuits-first release

TLDR

The IEEE Mixed‑Signal Technical Activity Committee is developing benchmark circuits for analog fault modeling, test generation, design‑for‑test, and built‑in‑self‑test, based on MITEL 1.5 µm and 1.2 µm CMOS technologies, to enable comparison of test results as in the digital domain. The paper aims to provide a set of typical circuits described by HSPICE netlists. These circuits are presented as HSPICE netlists. Schematic diagrams, simulation results, measured results when available, layout, and a typical test environment are provided.

Abstract

The IEEE Mixed-Signal Technical Activity Committee is developing a common set of benchmark circuits for use in researching and evaluating analog fault modeling, test generation, design-for-test, and built-in self-test methodologies. The first release circuits are based on MITEL Semiconductor's 1.5 /spl mu/m and 1.2 /spl mu/m CMOS technologies and they will allow engineers and researchers working in analog and mixed-signal testing to compare test results as is done in the digital domain. This paper presents a set of typical circuits described by netlists in HSPICE format. Schematic diagrams, simulation results and measured results, if available, are provided together with layout and a typical test environment. The full details are available on the web page dedicated to analog and mixed-signal benchmarks.